Referring to FIG. 1, a graph 20 of example waveforms of a conventional flip-flop is shown. The flip-flop may receive an input signal (i.e., D), receive a clock signal (i.e., CLK) and generate an output signal (e.g., Q). The flip-flop has a characteristic setup time (i.e., Tsu), a hold time (i.e., Th) and a clock-to-Q delay (i.e., Tco) relative to an active edge (i.e., AE) of the signal CLK. If the input signal is held steady through the setup time and the hold time, the output signal will represent the captured input signal after the clock-to-Q delay.
The clock-to-Q delay of the flip-flop is dependent on a signal setup (or arrival) time relative to the active edge. For larger signal setup times, the clock-to-Q delay is faster than for smaller signal setup times. Typical flip-flop characterization for setup times is done based on how far the clock-to-Q delay of the flip-flop pushes out at a particular signal setup time. Typically a fixed signal setup time is characterized as that time that produces a 10% increase in the clock-to-Q timing of the flip-flop compared with the clock-to-Q timing of an infinite signal setup time. The recorded clock-to-Q timing used for a Static Timing Analysis (STA) is the delay that corresponds to a “more than adequate” setup time. As such, a true delay through a flip-flop of a minimally setup signal will be 10% greater than the delay value commonly given to STA tools.
A global timing margin is commonly added across the circuit design in an attempt to compensate for issues, such as the 10% longer than expected clock-to-Q delay. In order to meet ever more challenging power and performance issues, the global margins are being deconstructed and eliminated. Further, the deconstruction yields issues, in terms of additional methods, that are added to compensate in specific terms rather than global terms. For example, tools are routinely used today that trade circuit speed for power. The circuits are slowed down by using slower but more power-efficient devices until the circuit just meets the timing criteria in order to save power. Such design activity is common for power reduction. However, side effects of slowing the circuit are increasing the number of ill-modeled paths and inducing a significant increase in undetected timing errors. A further problem with errors of such a nature is that the errors are difficult to debug when the design fails in the edge of a device-yield distribution.